(1) Field of the Invention
The present invention relates to a method for forming planarized insulating layers on semiconductor integrated circuits and more particularly, a method for leveling a multilayer borophosphosilicate glass (BPSG) at lower temperatures over patterned conducting layers on semiconductor substrates.
(2) Description of the Prior Art
Advances in semiconductor processing have reduced the minimum feature sizes on semiconductor integrated circuits to well below a half micrometer resulting in today's Ultra Large Scale Integration (ULSI) of circuits on semiconductor substrates. For example, improvements in high resolution photolithographic techniques have lead to submicrometer resolution in photoresist image sizes. The replacement of wet etching by directional (anisotropic) plasma etching allows the photoresist image to be replicated in the underlying multilayers of insulating and conducting layers that make up in part the semiconductor devices on the substrate. The accumulated effect of depositing these layers and the subsequent patterning of these layers, one layer on top of the other, result in substantially irregular or non-planar surface features on an otherwise microscopically planar substrate surface. The roughness of the topography worsens as the number of patterned layers increases on more advanced ULSI circuits, where the widths and spacing between patterned layers decrease. This rough topography is substantially worse at the later processing steps when the multilayer metallurgy is used to wire up the discrete devices on the integrated circuit chip.
These advancements in high resolution photolithography and anisotropic plasma etching have not come without certain technological problems. For example, the improvements in photolithographic resolution require large numerical aperture (NA) for the lens during optical exposure. This results in a more shallow depth of focus (DOF), and therefore causes unwanted distorted photoresist images over non-planar portions of the substrates. Further, anisotropic etching to pattern the various conducting layers over the non-planar surface can result in residue on the sidewalls of the underlying patterns, which can lead to intra-level shorts for conducting layers. In addition, thinning of narrow interconnecting metal lines over steps in underlying patterned layers can result in low yield and early failure of the circuit. This is especially true at high current densities where electromigration of the metal atoms in the line can lead to voids and open lines, or can result in extrusion of metal between the closely spaced lines leading to shorts. Another concern is the very shallow junctions that are required on ULSI Circuits to improve performance. This requires overall lower thermal budget (reduced temperatures and or anneal times) during processing to maintain the shallow junctions while also providing a planar insulating layer.
One method of forming a more planar dielectric layer involves depositing a relatively low-melting-temperature glass such as borophosphosilicate (BPSG), which is then annealed to level the layer. The degree of leveling can be improved by using higher temperature anneals for longer times and by increasing the dopant concentration of boron and phosphorus in the BPSG insulating layer, and/or increasing the thicknesses of the BPSG layer. However, as device feature sizes decrease for ULSI circuits, and more specifically the diffused junctions become shallower, it is essential to reduce the high temperature anneals and/or annealing times to reduce the overall thermal budget for processing the wafers. On the other hand, increasing the phosphorus and boron concentrations to lower the glass transition temperature (melting point) result in crystalline instabilities. Therefore, the upper limit of boron concentration is imposed by film stability. For example, BPSG with a concentration over 6 weight percentage (wt %) boron tends to be very hygroscopic and unstable, and therefore should be flowed immediately following deposition. At high dopant concentrations BPSG can also be an undesirable phosphorus diffusion source to the underlying silicon. This is particularly true at the higher boron concentration. Increasing the thickness of the BPSG layer increases the process times and adds to the manufacturing cost. An alternate method of planarizing the layer is to deposit an additional planarizing layer, such as-photoresist, and etching back, which is also more costly.
One method of reflowing the BPSG layer at lower temperatures is described in the prior art by Lee et al., U.S. Pat. No. 5,268,333. In this method, a first BPSG layer of lower concentration is formed over the resultant surface to a thickness of 6000 to 9000 Angstroms containing 3-4 wt % boron and 5-7 wt % phosphorus. A second BPSG layer of higher concentration is deposited over the resultant surface of the first BPSG layer having a thickness of 2000 to 6000 Angstroms and containing 4-7 wt % boron and 8-10 wt % phosphorus. This permits Lee et al. to lower the annealing temperature during reflow by as much as 50.degree. C. However there is still a concern with the instability of the highly doped BPSG.
Therefore, there is still a strong need in the semiconductor industry to further improve on the planarization process using a lower reflow temperature of BPSG with higher boron and phosphorus concentrations, while avoiding the crystalline instability at the higher dopant concentrations.